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Altera_Forum's avatar
Altera_Forum
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17 years ago

How to port design from QII 7.2SP3 to 8.1?

Hi,

I am trying to port a project from QII7.2SP3 to QII8.1 for its speed and incremental compilation. Here is how far I have gone:

1. Compiled the project in QII8.1 successfully, but the rpd doesn't work on my hardware.

2. Editted the megafunctions in QII8.1 and compiled successfully, the rpd still doesn't work.

Any comments? Thanks in advance.

Hua

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I remember there was a script available for porting designs/megafunctions from QII 7.2 to 8.0, does it have one for 8.1?

    Hua
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I'd check the "device and pin" options under the device menu in settings. Quartus likes to reset these to defaults at the least excuse. Otherwise I'd expect your bitfile to do something in your device.

    What sort of failure are you getting ? Failure to load the FPGA at all ? Gross malfunction or wierdness in normal operation ?
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thank you for your kind reply, drdr6.

    FPGA was loaded correctly, it even responded to my input correctly in the beginning, then it was totally lost. If I recycle the power, it comes back to life again to response to my input for a little while and then it is dead again.

    I post this question here just to see if anyone has gone down this path before ... it's too little information for anyone to help from distance.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Can you measure the current on your device ?

    One thing I am thinking: if your 8.1 has changed the default I/O assignment from input, highZ to output driving low, your device could be pulling a lot of current, getting hot and going out of spec.

    How long does it take for your device "to be lost" ? milliseconds, seconds or minutes ? How do you tell ?
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    This problem has been fixed a while back but forgot to come back to post the result.... thought someone may have the similar problem.

    It was caused by a floating sigal in the design, which went unnoticed in 7.2 sp3 but got caught in 8.1. Apparently QII 8.1 assigned a value to this floating signal and locked the part of the logic that took it into the equation. Once I cleaned this part of the code, the design was working again.

    Thanks for drdr6's reply along the way.