How to perform logical operation for two signal generated at diiferent clock cycle?

I have a verilog code for memeory.I got the output for presynthesis,but postsynthesis i'm unable to get the simulation rersult

This is my actual code for memory...............

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`timescale 1ns/100ps

module main( sysclk, reset,read_out);

//<statements>

input sysclk;

input reset;

output read_out;

reg [7:0] count1_1,count2_1;

reg [7:0] count12_1,count11_1;

wire [7:0]count11,count12,count1,count2;

reg count1_en,count2_en,count11_en ,count12_en;

//////////////////////////////////////

//////////////DATA FOR MEMORY1

///////////////////////////////

// counter1

always @( posedge sysclk)

begin

if (reset==0)

begin

count11_en <= 1;

count11_1<= {8{1'b0}} ; end

else

if(count11_en == 1)

if(count11!= 8'd222)

count11_1<= count11_1 + 1;

if(count11_1== 8'd222)

begin

count11_en <= 0;

count11_1<=8'd0;

end

end

assign count11=count11_1;

always @( posedge sysclk)

begin

if(count11==0) begin

count12_en <= 1;

count12_1 <= {8{1'b0}} ; end

else

if(count12_en == 1)

if(count12_1!= 8'd222)

count12_1 <= count12_1 + 1;

if(count12_1==222)

begin

count12_en <= 0;

count12_1<=8'd0;

end

end

assign count12=count12_1;

wire[7:0] read_out1;

//////////////////////////////////////////////////////////////////////

// Instantiate Unit Under Test: memory1

//////////////////////////////////////////////////////////////////////

memory1 memory1_0(

.WD(count11),

.RD(read_out1),

.WEN(count11_en),

.REN( count12_en),

.WADDR(count11),

.RADDR(count12),

.WCLK(sysclk),

.RCLK(sysclk),

.RESET(reset)

);

..................................................................

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Warning: (vsim-3017) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): [TFMPC] - Too few port connections. Expected 9, found 7.

#

# Region: /tb_mem/main_0/memory1_0

# ** Error: (vsim-3063) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): Port 'read_out1' not found in the connected module (1st connection).

#

# Region: /tb_mem/main_0/memory1_0

# ** Error: (vsim-3063) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): Port 'count11_1' not found in the connected module (2nd connection).

#

# Region: /tb_mem/main_0/memory1_0

# ** Error: (vsim-3063) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): Port 'count12_1' not found in the connected module (3rd connection).

#

# Region: /tb_mem/main_0/memory1_0

# ** Error: (vsim-3063) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): Port 'count11_en' not found in the connected module (4th connection).

#

# Region: /tb_mem/main_0/memory1_0

# ** Error: (vsim-3063) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): Port 'count12_en' not found in the connected module (5th connection).

#

# Region: /tb_mem/main_0/memory1_0

# ** Error: (vsim-3063) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): Port 'sysclk_c' not found in the connected module (6th connection).

#

# Region: /tb_mem/main_0/memory1_0

# ** Error: (vsim-3063) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): Port 'reset_c_0' not found in the connected module (7th connection).

#

# Region: /tb_mem/main_0/memory1_0

# ** Warning: (vsim-3722) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): [TFMPC] - Missing connection for port 'WD'.

#

# ** Warning: (vsim-3722) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): [TFMPC] - Missing connection for port 'RD'.

#

# ** Warning: (vsim-3722) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): [TFMPC] - Missing connection for port 'WEN'.

#

# ** Warning: (vsim-3722) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): [TFMPC] - Missing connection for port 'REN'.

#

# ** Warning: (vsim-3722) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): [TFMPC] - Missing connection for port 'WADDR'.

#

# ** Warning: (vsim-3722) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): [TFMPC] - Missing connection for port 'RADDR'.

#

# ** Warning: (vsim-3722) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): [TFMPC] - Missing connection for port 'WCLK'.

#

# ** Warning: (vsim-3722) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): [TFMPC] - Missing connection for port 'RCLK'.

#

# ** Warning: (vsim-3722) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): [TFMPC] - Missing connection for port 'RESET'.

#

# Error loading design

# Error: Error loading design

# Pausing macro execution

# MACRO ./run.do PAUSED at line 16

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the above mentioned error i got during postsynthesis simulation i'm not getting how to solve this error please help in this...........

i'm using libero Soc11.4v software to write and code and modelsim microsemi 10.3c simulator .

please help to solve this problem