How to perform logical operation for two signal generated at diiferent clock cycle?

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Hi everyone,

i have to random binary data signal,one starts at 100ns and ends at 1450ns ,another data signal starts from 14350ns and ends at 15000ns. I want perform xor operation of these two data signal in verilog.How to shift the signal or how to make the second data signal to start from 100ns so that both signal have data at the same at same clock cycle?.please help me....i'm new to this verilog code.

thank you.

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one way is to use two fifos, one dual clk on clk1/clk2, the other single on clk1. once both have data read out and xor.

Or use handshake approach instead of fifo but a shallow fifo is almost same cost as handshake.