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Altera_Forum
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11 years ago

How to optimize the Nios embedded system address usage ???

In the nios embedded system design, Nios needs to connect with a onchip_ram (used for data and instrucation) and a jtag_uart. I always have these two IPs in my design with nios processor to compose a minimum system.

Then I have other periperals like DDR3, what I usually did is connect these periperals with an Avalon mm bridge, then connect to Nios. But the address bus of mm bridge needs to be configured, either 30 or 31 bits, which means is 1GB or 2GB. The address range of nios II is 2GB. So this brings a problem about address waste.

Assume I want to connect a 1GB DDR3 to nios, in this case, what I always did is I set the MM bridge as 1GB, then Nios has 1 GB left, I connect onchip_ram, jtag_uart directly with Nios since I don't think connect them with bridge to Nios is a good idea (may reduce speed?) But if I have other peripherals need to connect, I can't connect them with MM bridge since DDR3 always occupies all the range. In this case, I have following choice:

1. Expand the MM bridge to 2 GB, all the peripherals include onchip ram, jtag_uart connect with MM bridge firstly.

2. Connect other peripherals directly to Nios.

3. Add another MM bridge with 512 MB range, then connect other peripherals to it.

The 1st and 2nd approach can use all the address, but 2nd approach may have too many peripherals connect to Nios directly. The 3rd approach will cause some wastes. So which approach can bring the best performance?

Thanks.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    I'd take out your MM bridges - especially the one to the DDR3 memory.

    You might need one between the nios and other 'slow io', but only if you have Fmax issues.

    Some Altera projects have an MM bridge before the JTAG UART - probably to get rid of timing errors that used to be reported inside it.

    More interesting than an MM bridge, would be a conduit that ignored a lot of the address lines.

    Then you could put your DDR3 at 1G-2G with everything else between 0 and 1M (or lower) aliased 1024 times.