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Altera_Forum's avatar
Altera_Forum
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11 years ago

How to optimize the Nios embedded system address usage ???

In the nios embedded system design, Nios needs to connect with a onchip_ram (used for data and instrucation) and a jtag_uart. I always have these two IPs in my design with nios processor to compose a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I'd take out your MM bridges - especially the one to the DDR3 memory.

You might need one between the nios and other 'slow io', but only if you have Fmax issues.

Some Altera projects have an MM bridge before the JTAG UART - probably to get rid of timing errors that used to be reported inside it.

More interesting than an MM bridge, would be a conduit that ignored a lot of the address lines.

Then you could put your DDR3 at 1G-2G with everything else between 0 and 1M (or lower) aliased 1024 times.