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Altera_Forum's avatar
Altera_Forum
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13 years ago

How to negedge trigger the IP module?

In Quartus II, it seems all the sequential IP modules are triggered by postive edge. If I want to trigger them using negative edge, how can I do except I put a not gate in clock? I don't think ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I think you are right. Pll can provide exact 90 degree shift clock. We can't edit ip core.

Thanks very much.