Forum Discussion
New ContributorHow to mitigate excessive I/O pins fitter error
I am trying to compile a RISC-V core in Quartus (Pro 19.2), specifically the SweRV EH1 from Western Digital (https://github.com/chipsalliance/Cores-SweRV). I was able to get synthesis to pass with only one extra trick required (https://community.intel.com/t5/Intel-Quartus-Prime-Software/Getting-Synthesis-Error-due-to-undefined-Macros-In-quartus-pro/m-p/661513#M61117 ), but now the fitter is failing due to too many user I/O pins being required. According to the error, the "design requires 1417 user-specified I/O pins" while there are only 624 available on the Arria 10 GT 1150 that I am targeting. This seems to be quite an excessive number of I/O pins required (more than double what is available on a decent sized FPGA), so I am assuming that somewhere in the compilation flow Quartus is finding/creating pins that really shouldn't be I/O, as I can't imagine this design really needs so many pins.
So I guess my questions are, is this a reasonable assumption that Quartus might be to blame for these excessive I/O pins? And if so, how could I go about fixing this, and/or convincing Quartus that there really aren't so many I/O pins required?
Thanks!
6 Replies
AminT_IntelRegular Contributor
Hello,
I don't think it possible to fix this issue with device that you have. Our FPGA devices have different pins available so I will advice you to check your design so it can fit with your FPGA device. You could also try different FPGA devices to fit with your design.
I hope this answer helps. Stay safe!
rlb1116Do any Intel FPGAs support 1400+ user I/O pins? I imagine probably not, seeing as how the Arria 10 1150 (which is not small) has significantly less than that at only 624.
I don't think the problem is that the device has insufficient pins, but rather that a large majority of the 1417 ports "requiring" an I/O pin don't actually need to be seen outside of the FPGA as input or output. A RISC-V core certainly shouldn't need 1400 physical I/O connections.
So my question is more along the lines of, how can I parse the ports identified as I/O down to those which actually need to reach outside of the chip? Assuming I am able to identify these truly necessary I/Os in the design, how do I tell Quartus to ignore the others? Are there any compilation tricks for this or do I need a higher-level wrapper with just the essentials? (The design came with a wrapper as the top-level entity, but this induces the 1400 I/O ports, most of which I believe should not be physical I/Os.)
- sstrell
Super Contributor
Look at the top-level HDL code and/or the Pin Planner (Assignments menu) All Pins list to see all the top-level I/O required for the design. Quartus would not add any additional pins to the design unless you edit the code.
