New Contributor
New ContributorDo any Intel FPGAs support 1400+ user I/O pins? I imagine probably not, seeing as how the Arria 10 1150 (which is not small) has significantly less than that at only 624.
I don't think the problem is that the device has insufficient pins, but rather that a large majority of the 1417 ports "requiring" an I/O pin don't actually need to be seen outside of the FPGA as input or output. A RISC-V core certainly shouldn't need 1400 physical I/O connections.
So my question is more along the lines of, how can I parse the ports identified as I/O down to those which actually need to reach outside of the chip? Assuming I am able to identify these truly necessary I/Os in the design, how do I tell Quartus to ignore the others? Are there any compilation tricks for this or do I need a higher-level wrapper with just the essentials? (The design came with a wrapper as the top-level entity, but this induces the 1400 I/O ports, most of which I believe should not be physical I/Os.)
Super ContributorLook at the top-level HDL code and/or the Pin Planner (Assignments menu) All Pins list to see all the top-level I/O required for the design. Quartus would not add any additional pins to the design unless you edit the code.
