--- Quote Start ---
I've implemented sigma delta ADC on cyclonII DE1 FPGA.
the analog input is digitized at the multi-bit output (some pics attached)
now I want to evaluate the output by measuring the Signal to Noise Ratio (SNR) and ENOB and power spectrum but I dont know how to do that in practice?
using which software or which device ?
and how to get the diagrams for SNR and Power spectrum?
can anybody guide me?
--- Quote End ---
Here's an example of ADC characterization:
http://www.ovro.caltech.edu/~dwh/carma_board/digitizer_tests.pdf Here's more notes of similar material:
http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-104paper_hawkins.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-104slides_hawkins.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf For testing your design, you can capture a series of samples of a sinusoid or noise signal (see the LFSR document for a noise generator).
You can then use a package like MATLAB or Octave to create histograms of samples. Those histograms can then be summed to create a cumulative distribution function (CDF). The CDF can then be inverted to determine 'where' the ADC decision logic changed codes. This provides the stair-case voltage-to-digital code transfer function of the ADC. From that plot you can generate INL/DNL curves.
If you generate the input signal using a DAC with more bits than then ADC, you can generate a noise signal with a notch. The depth of that notch in the digital power spectrum is determined by the 'noise power ratio' (NPR). The ideal NPR for different bit widths is in here ...
http://www.ovro.caltech.edu/~dwh/wbsddc/correlator_efficiency.pdf Just look at the pictures in these references, and then start writing some code to analyze your data. As you write your code, you'll start to find the useful bits in these documents.
Cheers,
Dave
Honored Contributor
