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Altera_Forum's avatar
Altera_Forum
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8 years ago

how to map many ports to a vector/array ?

Hi All, I have an entiry with a lot of ports. I'd like to map these ports to a vector/array. example: Ports: bit_000_0 : in std_logic; bit_000_1 : in std_logic; bit_000_2 : in ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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Concatenation:

vec(4 downto 0) <= bit_000_4 & bit_000_3 & bit_000_2 & bit_000_1 & bit_000_0

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Could this assignment be done in the package? Remember that bit_000_4, bit_000_3, ... are ports - could they be observed from a package?