how to map many ports to a vector/array ?

Hi All,

I have an entiry with a lot of ports. I'd like to map these ports to a vector/array.

example:

Ports:

bit_000_0 : in std_logic;

bit_000_1 : in std_logic;

bit_000_2 : in std_logic;

bit_000_3 : in std_logic;

bit_000_4 : in std_logic;

Desired mapping of the ports to a vector:

vec (0) <= bit_000_0;

vec (1) <= bit_000_1;

vec (2) <= bit_000_2;

vec (3) <= bit_000_3;

vec (4) <= bit_000_4;

Can I use a function/package for this purpose? There are a lot of such ports (~150), so I'd like to do these assignments in the separate file (e.g. package) and do not clutter the top entity/module file. Is this possible?

Thank you!