Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

How to make timing constraint in this case??

Hi all, I've used a counter to make a clock enable such that I could get a new clock with divided frequency. The waveform is shown as below. Because there must be some clock skews for the coun...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Yes, I know what you mean kaz.

But it sounds to me like you are saying the clock edge are always arriving different registers at the same time.

I am thinking of the case for the path to the counter register, we get an early clock. But for the path to another register which will need to be clock-enalbed, it gets a late clock edge.