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Altera_Forum's avatar
Altera_Forum
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14 years ago

How to make timing constraint in this case??

Hi all, I've used a counter to make a clock enable such that I could get a new clock with divided frequency. The waveform is shown as below. Because there must be some clock skews for the coun...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

if a clock edge happened to be late then enable generated will be late. because enable is generated locally on register (of counter). So why worry, both would be late and next clock edge will be late and will read the late enable correctly. It is safe and proven for decades.