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Altera_Forum's avatar
Altera_Forum
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14 years ago

How to make timing constraint in this case??

Hi all, I've used a counter to make a clock enable such that I could get a new clock with divided frequency. The waveform is shown as below. Because there must be some clock skews for the coun...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The enable signal is still a register right, it is possible that the enable is driven to low by a early clock rising edge. And enable signal then is propagated to another register and that register received a late clock rising edge. That caused the late clock rising edge failed to be enabled at that register