How to make timing constraint in this case??

Yes, I am using it as an enable;

I write the verilog code like this:

always@(posedge oclk or negedge rst)

begin

if(~rst_n)

begin

...

end

else if(oclk_enable)

begin

...

...

end

else

begin

...

end

end

Is it the right way? But I think because the oclk has some sort of skew(even if it's generated out of a pll), it is still possible that some branchs of oclk rising edge arrive late and miss the enable.