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Altera_Forum's avatar
Altera_Forum
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14 years ago

How to make timing constraint in this case??

Hi all, I've used a counter to make a clock enable such that I could get a new clock with divided frequency. The waveform is shown as below. Because there must be some clock skews for the coun...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I am afraid you are on the wrong path. you don't generate a clock like that. Normally you avoid generating clock from logic gating as you get all sorts of problems.

You are supposed to use the enable as enable not as clock. i.e. don't connect it to clock port of registers. Then you don't need to worry about timing as it will be synchronised with clk that generates it from the counter.