How to make Questa show delays through gates?

Good question, Mark. The core issue is that the .vo netlist Quartus generates is a structural (technology-mapped) netlist, but without SDF back-annotation it simulates functionally — gate delays are zero (or unit) delay by default, so you won't see them in the Wave view. Here's what you need to do:
1. Generate and apply the .sdo (SDF) file
The EDA Netlist Writer can generate a Standard Delay Output (.sdo) file that includes back-annotation of delays for a design's netlist for use during simulation. Although the .sdo only contains delay estimates and imprecise timing information, including the .sdo in simulation results in a more accurate simulation output. Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation The .sdo file requires that the .vo netlist is compiled in the project, because the .vo file instantiates the primitives needed for timing simulation. Compiling only the RTL .v file and applying the .sdo without the .vo netlist will cause errors. Why do I get the error "SDF files require Altera primitive library" when I try to load my design in ModelSim? The SDO file must be applied to the entity in the VO file (not the top-level testbench entity). To do this in the Load Design dialog, click the SDF tab, add the SDO file, and in the 'Apply to Region' box type the path of the instance in the VO file. Why do I get a "Failed to find INSTANCE '/instance_name'" error when performing a timing simulation in ModelSim simulator?
On the command line, use the -sdftyp switch in your vsim command, for example:
vsim -t 1ps -L -sdftyp /i1=your_design.sdo work.your_testbench +transport_int_delays +transport_path_delays
2. Enable transport delay options
By default, the simulator filters out all pulses that are shorter than the propagation delay between primitives. Turning on the transport delay options prevents the simulator from filtering out these pulses. Quartus® II Handbook Version 13.1 This is critical if your inserted combinational delays are producing short pulses.
Use +transport_path_delays when simulation pulses are shorter than the delay in a gate-level primitive (you must also include +pulse_e/number and +pulse_r/number). Use +transport_int_delays when simulation pulses are shorter than the interconnect delay between gate-level primitives (you must also include +pulse_int_e/number and +pulse_int_r/number). Quartus® II Handbook Version 13.1
3. Important limitation to be aware of
The EDA Netlist Writer currently supports .sdo file generation only for Verilog .vo simulation in the QuestaSim simulator (not Questa Intel FPGA Edition) for Stratix 10 designs. The EDA Netlist Writer does not currently support .sdo file generation for any other simulator or device family. Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation
So whether this flow is available to you depends on your device family and which edition of Questa you're using. If you're on Questa-Altera FPGA Edition and a non-Stratix 10 device, the .sdo generation path isn't supported, and you'd need to use a standalone QuestaSim (or Questa Core) license with a Stratix 10 design to get full SDF back-annotation.
In summary: make sure you're loading the .vo (not just your RTL), applying the .sdo via -sdftyp, and passing the +transport_*_delays switches to vsim.

Note: To continue using AI Responder, please start your next inquiry with ai_responder

Disclaimer (Beta): The AI Responder is currently provided as a beta feature. AI-generated responses may contain errors or omissions. Please verify technical guidance with official Altera documentation before implementation.

Thank you very much.

Questa no longer supports gate delays. Previously, this was possible using .sdo files, but that support has been discontinued. For timing analysis, you will now need to rely solely on the timing analyzer.