How to let customers update the FPGA firmware

You haven't really provided enough information;

1. What does your FPGA configure from? Eg., AS mode from EPCS flash, PS mode, FPP mode, etc.

2. What happens if the FPGA image gets corrupted? Is the board bricked, and in need of a USB-Blaster to recover?

3. Can you support two configuration images, eg., two images, "last known good" and "new", or perhaps "factory safe image" and "customer image".

Cheers,

Dave

The current design configures from an EPCS4SI8 device using AS.

I would add a JTAG 10 pin connector for a second method of programming at our factory.

I could support two images. Since I will re-design this board, I can be open to changes.

Have you already reviewed the ALTREMOTE_UPDATE material?

http://www.altera.com/literature/lit-config.jsp

Since you have a NIOS, you also have the option of simply rewriting the EPCS from software (open the device like a traditional serial flash).

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The current design configures from an EPCS4SI8 device using AS.

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Ok, the EPCS devices are SPI Flash. Micron and others supply similar parts at much lower cost. You could use a part that could support two images.

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I would add a JTAG 10 pin connector for a second method of programming at our factory.

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Its always a good idea to include the Altera JTAG header as it provides a debug interface to your board. The EPCS device can be programmed via the FPGA using JTAG indirect mode, there is no need for an Active Serial header.

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I could support two images. Since I will re-design this board, I can be open to changes.

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Review the remote update block. I haven't used that IP, but I do recall you can change the MSBs of the address used to access the EPCS flash, i.e., you can change where the FPGA loads its configuration image from within the flash. Your task will be to determine how to configure that IP so that it first attempts to load from the customer flash area, and if that fails, tries to configure from the factory area.

Cheers,

Dave

The Altera API functions for writing to EPCS aren't entirely ideal.

Mostly because they always erase the flash sector before doing a write (even if the area being written is all 0xff).

That means that you have to have a large buffer available - which may be a problem if you don't have external memory.

I would dig down a couple of layers of functions and use the lower level ones (or write equivalent ones that are smaller and faster).

Another problem is that you don't seem to be able to get the EPCS SPI block without having the EPCS boot code. I don't know if it is possible to get the boot code memory optimised away by using a conduit to force the address lines to desect it.

I also suspect the nios could bit-bang the raw SPI pins fast enough.