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Altera_Forum
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15 years ago

How to interconnect modules without 'valid' or 'done' output signal

I have a design which does single precision computations using Altera Floating point IPs. However since these IPs don't seem to have a 'valid' or 'done' output bit, I'm not able to see how to connect...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Can you tell me where did you read the 6 cycles delays between the subsequent inputs and the results?

I'm trying to read the "Floating-Point Megafunctions

User Guide" and still found nothing.

Thx