How to interconnect modules without 'valid' or 'done' output signal

But there are two different delays for an IP:

The delay between first input and output and the delay between subsequent outputs assuming inputs are being given every clock cycle.

For example for the exponential core,

there is a latency delay of 17 clock cycles between the first input and output but subsequent outputs appear at intervals of 6 clock cycles(not every next clock cycle) assuming new input data is being given at every clock cycle. Hence I was thinking that there will be a point where probably the buffer or whatever the mechanism inside the IP is, will be overflown by the input data. Am I correct in my understanding? Thanks.