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Altera_Forum
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15 years ago

How to interconnect modules without 'valid' or 'done' output signal

I have a design which does single precision computations using Altera Floating point IPs. However since these IPs don't seem to have a 'valid' or 'done' output bit, I'm not able to see how to connect...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

If the design is fully pipelined there's no buffer.

it can process a new input for every clock cycle.

After an initial delay, the IP provides an output for every clock cycle.