How to interconnect modules without 'valid' or 'done' output signal

So what I understand:

1-Instantiate IP in module

2-Also make a shift register to implement the latency delay of your IP

3-The shift register holds a '1' for the 'valid' bit which gets successively gets shifted and is finally given as output.

Right?

Also what is the buffer capacity of the IPs, if I keep giving new data in every clock cycle, how long before I have to stall the input data before the IP starts giving wrong outputs?