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Altera_Forum
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15 years ago

How to interconnect modules without 'valid' or 'done' output signal

I have a design which does single precision computations using Altera Floating point IPs. However since these IPs don't seem to have a 'valid' or 'done' output bit, I'm not able to see how to connect...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The "parallel" valid bit chain is simply a shift register (respectively a number of cascaded D-FFs), the delay (number of stages) is equal to the pipeline delay of the respective IP block.

I aggree, that Altera could have added it as an option, but as mentioned above, it won't be of any use in the standard application, where a continous data stream is fed to the IP.