How to instantiate or infer glitch free clock mux for Stratix10 device?

Hi @RDevk​

I tried using clock control IP for Stratix10 device for clock mux logic but what I see in post-fitting netlist is that clock mux is mapped to ALUT. Does Stratix10 device has hard glitch free clock mux?

==> No

Is there a way to tell the Quartus tool with some HDL synthesis attribute to infer glitch free clock mux?

==> I guess you are referring to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii51007.pdf (Example 13-48)

How can I implement glitch free clock mux in Stratix10?

==> Same as above. See example 13-48.

Other question is that if logic in the design is clocked by output of clock mux can Quartus STA do analysis by propagating both the clocks at the input of clock mux? How do we have to add set case analysis?

==> Let me check with timing expert and get back to you.

Hi @RDevk​

Follow up on your last question.

You would need to constraint it correctly for a correct Timing analysis.

See: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf (Figure 7 Example 9)