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Ruturaj_D_Intel
New Contributor
New ContributorHow to instantiate or infer glitch free clock mux for Stratix10 device?
Hi, I tried using clock control IP for Stratix10 device for clock mux logic but what I see in post-fitting netlist is that clock mux is mapped to ALUT. Does Stratix10 device has hard glitch free c...
JonWay_altera
Frequent Contributor
Frequent ContributorHi @RDevk
Follow up on your last question.
You would need to constraint it correctly for a correct Timing analysis.
See: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf (Figure 7 Example 9)
