Forum Discussion
Altera_Forum
Honored Contributor
14 years agoYes.
It's important to use the FPGA's clock input pins for clocks. Put simply, the global/regional clock distribution networks can't be driven by generic I/O pins. Neither the PLLs. For more details, read the Stratix III's handbook chapter on clocking resources. Depending on your need, you might get away with it and make it work. But sometimes, it's just impossible to meet timings with clocks coming from generic I/Os.