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Altera_Forum's avatar
Altera_Forum
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18 years ago

How to initial counter value?

I am trying to initial counter value, but fail... 

if(rising_edge(clk)) then
  if(sload = '1') then
     s_cnt <= 5;
  elsif(count_en = '1') then 
     s_cnt <= s_cnt + 1;
  end if;
end if;

I look into Technology post-fitting netlist view, and find that 'sload' is connected to all the registers 'sclr' pin of the counter.

I know this should be a stupid question, but hope for any response still.

Thanks in advance...

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    I tried to duplicate your issue but couldn't. Some of the bits in s_cnt (I gave it a natural type because you didn't specify) use s_clr. You're loading 5, which requires s_cnt[2] and s_cnt[0] to sload VCC, or Quartus II could simply avoid using sload for those bits and put the logic in the d-input cone. That's what I'm seeing in Quartus II 7.2 for a Stratix II device.

    Are you sure it uses slcr for ALL bits? If Quartus II uses NOT-gate push-back (invert register input and output), it could use sclr for those bits, too. It would change the power-up state of the registers, which is probably unspecified in the design.

    Have you enabled/disabled any special settings? What version of Quartus II? What device? Have you done a timing simulation to verify the behavior is incorrect?

    In general, I'd be careful about analyzing the design on the FPGA. There are tons and tons of tricks and optimizations that may look wrong but are, in fact, just clever and correct. :)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Thanks for your response...

    In fact, when I set the module as top-level module than do a full compilation, the result is what I want: s_cnt[0] & s_cnt[2] were loaded with VCC and the other registers were loaded with GND.

    But when I fully compile my whole system which contain the counter module as sub-module, the result change, sload connect the sclr pin of all the register.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    I have found the bug.

    It is something related to VHDL configuration syntax.

    Thanks for the help.