How to initial counter value?

I tried to duplicate your issue but couldn't. Some of the bits in s_cnt (I gave it a natural type because you didn't specify) use s_clr. You're loading 5, which requires s_cnt[2] and s_cnt[0] to sload VCC, or Quartus II could simply avoid using sload for those bits and put the logic in the d-input cone. That's what I'm seeing in Quartus II 7.2 for a Stratix II device.

Are you sure it uses slcr for ALL bits? If Quartus II uses NOT-gate push-back (invert register input and output), it could use sclr for those bits, too. It would change the power-up state of the registers, which is probably unspecified in the design.

Have you enabled/disabled any special settings? What version of Quartus II? What device? Have you done a timing simulation to verify the behavior is incorrect?

In general, I'd be careful about analyzing the design on the FPGA. There are tons and tons of tricks and optimizations that may look wrong but are, in fact, just clever and correct. :)