Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

How to Import whole the truth table into Quartus and automatically Optimize it

Hi every one I had designed a Combinational circuit in Quartus II 13.0 but it was not optimized as the number of input variables were so many I couldn't simplify it using Karnaugh Maps ,so I dec...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

--- Quote Start ---

yes thx dear but how about the Optimized circuit after compile? can you extract the VHDL code of the Optimized version of your code?

--- Quote End ---

The netlist is not vhdl and I don't know of conversion from netlist to schematic.

However as mentioned a rom table will do in schematic. Your input will be the address. The contents will be the output e.g. for above example

location 0 of rom should contain 1011 and soon.