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Altera_Forum
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12 years ago

How to Import whole the truth table into Quartus and automatically Optimize it

Hi every one I had designed a Combinational circuit in Quartus II 13.0 but it was not optimized as the number of input variables were so many I couldn't simplify it using Karnaugh Maps ,so I dec...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

If I am given truth table to design in vhdl I will use case statement and expect the tool to do the rest old techniques.

e.g.

A B C D E F out1 out2 out3 out4

0 0 0 0 0 0 1 0 1 1

...

case input is

when "000000" => out <= "1011";

...

with a bit of concatenation