Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

How to Import whole the truth table into Quartus and automatically Optimize it

Hi every one I had designed a Combinational circuit in Quartus II 13.0 but it was not optimized as the number of input variables were so many I couldn't simplify it using Karnaugh Maps ,so I dec...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

The Karnaugh Map has no sense on fpgas because it is oriented to AND-OR-NOT gates. In fpga you have 4-inputs look up tables. A way to implement a truth table when you can't describe with a logic expression or can't find a vhdl description, is an asynchoronous rom description in vhdl or veriflo and a lot of time to fill each row.