How to implement a System like this easily using Altera Tools of my DE1-SOC?

Do you want to write software or HDL?

If you want to write HDL, then create a new Qsys component IP block and instantiate it four times. Give it however many Avalon-ST ports necessary to make your connections. Use e.g. Modular SGDMA to read the frame data out of RAM and supply it to the components, and have a NIOS with software to control the flow and manage the DMA.

If you want to write software, something as simple as a large shared on-chip RAM with (4) NIOS connected directly to it would work. Qsys would automatically take care of arbitration/contention, but since you don't have a speed requirement this is fine.