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areebTAG's avatar
areebTAG
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3 years ago

How to implement a custom IP component in Quartus Prime 21.1 ?

Hi, I am using the DE1-SoC board and trying to add a custom component in the platform designer. I used the GHRD that came with the board. I added a screenshot for this. However, what I am suppo...
areebTAG's avatar
areebTAG
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3 years ago

I am waiting for your answer

sstrell's avatar
sstrell
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3 years ago

I'm not support. I'm a guy on the internet.

Your design files for simulation and synthesis don't have to be exactly the same. Just use a single bit for 1 for synthesis. You'll get warnings in Quartus about mismatched bit widths, but you can ignore that.

If area optimization didn't work, I'm not sure what else to tell you. Your design is just too big for this device.

  • areebTAG's avatar
    areebTAG
    Icon for New Contributor rankNew Contributor
    3 years ago

    Its okay now the problem is fixed. I simply replaced some of the large variables with signals and now the design fits. Can you tell me about block RAM and what name I need to use so the synthesizer can identify it?