New Contributor
Super ContributorLABs are logic array blocks. And yeah, your design is simply too big for the device you're targeting. It really was that simple! This design along with the Platform Designer interconnect needed to support it and connect to the HPS is too much for this device.
Your code looks pretty good. I don't see a lot of deep embedded if statements other than for your control signals, which is good.
But you do have large 64 bit functions and large loop iteration counts.
And why do you need 64 bits to represent "one"?
Try enabling Aggressive Area optimization in the Compiler Settings (that may be in Pro since that's what I normally use, but there should be a similar setting in Standard).
New Contributor"And why do you need 64 bits to represent "one"? "
This is because I can't figure out a way to perform computations using 64-bit values with the number 1 as B"01", if I try that then I see a "X" symbol in Questasim. If you have a better idea then let me know, that could be the difference lol.
I tried the aggressive area setting and after 20 minutes of misery it yielded no results. What is your advice for modifying my code so it can fit?
New ContributorI am waiting for your answer
Super ContributorI'm not support. I'm a guy on the internet.
Your design files for simulation and synthesis don't have to be exactly the same. Just use a single bit for 1 for synthesis. You'll get warnings in Quartus about mismatched bit widths, but you can ignore that.
If area optimization didn't work, I'm not sure what else to tell you. Your design is just too big for this device.
New ContributorIts okay now the problem is fixed. I simply replaced some of the large variables with signals and now the design fits. Can you tell me about block RAM and what name I need to use so the synthesizer can identify it?
