New Contributor
Super ContributorSo you created your custom component and used the Component Editor to bring it into PD. Does your custom component require I/O pins? If so, you would need to export those signals from the component, usually by setting those signals as part of a conduit interface and then exporting from PD.
Did you make adjustments to the HPS I/O pin usage in the HPS parameters?
Also, did you intend to connect your custom component to the lightweight bridge of the processor (usually used just for CSR access of a component) or should you be enabling the regular h2f bridge for high-speed data transfer?
Maybe more detail of what your design goal here is would be helpful. Also, exact error messages from the tool would help as well.
New ContributorHi I get error messages about "design too large to fit in device". How can I modify my VHDL circuit to fit inside the FPGA, for example do I need to work on reducing variables, signals or process blocks etc?
My VHDL circuit has been tested many times with testbench in Questasim and works as expected but cannot seem to synthesized.
Please reply I am waiting.
Super ContributorAgain, more info needed, maybe some code snippets or screenshots of all the error and warning messages you are getting. Just saying "design too large to fit in device" without any context of other messages, compilation report details, or code makes it very difficult to figure out what's going on. You also mentioned you get errors about pin assignments. What are those errors?
You could also try synthesizing the code outside of the Component Editor directly in Quartus. Create a dummy project and set your custom design as top-level. See if you get more detailed info about any issues with your design when you do that.
New ContributorOk I will try the dummy project approach, meanwhile I attached my entire error log and VHDL code. Have a look.
