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I would connect your cpu directly to a dual ported internal memory block (use the other port for everything else) then you don't need to worry about wait states (generated by the memory block).
The memory will do a read every clock - the 'data out' is valid in the cycle following the address.
For writes the address, data and write enable are valid in the same clock (a read happens as well).
If you are pipelining reads (as the nios does) then you end up having to add a wait state when a write follows a read.
There is also a clock enable/address hold signal, the nios uses this to keep the correct address valid when the cpu stalls because the previous cycle stalls on the avalon bus - since the address gets updated by the following instruction.
If you use signaltap to watch a nios cpu accessing tightly coupled data memory, you see that it does the read cycle regardless of the opcode value.
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I will look into it. I should change my CPU, since it expects the memory to be there on the same clock cycle that it is needed. I don't have caches so I guess I need to stall my CPU every time the access is needed.
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