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Altera_Forum's avatar
Altera_Forum
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13 years ago

How to identify if your design has a race condition.

I am currently working on a CPU and I managed to make it run an sequence of instructions (All it does is add 1 to a register and then store it into a memory mapped device which controls LEDs on my FP...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Ok I am asking another question. I am testing out the memory unit in my CPU (for reads/writes) and I am having the exact same issue for reading. Is there any provisions I can do to insure that this doesn't happen and that the pipeline stalls when the read takes too long? I have currently implemented a wait request signal so I am not sure as to what I should also put. Maybe a data valid signal?