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Altera_Forum's avatar
Altera_Forum
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13 years ago

How to identify if your design has a race condition.

I am currently working on a CPU and I managed to make it run an sequence of instructions (All it does is add 1 to a register and then store it into a memory mapped device which controls LEDs on my FP...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

You can create tightly coupled memory cores from the Nios2 configuration window in QSys. (IIRC its in the tab with the other memory and cache parameters).

With on-chip memory, using a clock that is 4 times the one of the CPU will probably not make things go faster. It will probably even be slower, because of the clock domain crossing logic that QSys will add. The most efficient way should be to use the same clock on both the CPU and the on-chip memory.