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What sort of design approach are you taking?clo
With good synchronous design there should be no 'race' conditions as everything is driven off the same clock (at the simplest level).
Nial
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What do you mean by design approach?
What I can tell you is that the main clock is fed into a PLL which produces a second clock. That clock is syncronized with the main clock so all clocks are synced properly.
To me it looks like it is an issue with the instruction fetching hardware or something like that. The CPU seems to completely freeze. Maybe it just skipped fetching an instruction or something like such.
Honored Contributor
