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Altera_Forum's avatar
Altera_Forum
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9 years ago

How to handle too many pins in the design when migrating from Cyclone to Cyclone III

Hi, I have an old design for EP1C12Q240 device that I want to migrate to EP3C25Q240.

The old design uses all available IO pins i the device. Now I want to migrate the design to EP3C25 device, which has less IO pins.

I want to keep the design unchanged, I just want leave some of the internal ports unconnected to any of the physical IO pins.

What is the best way to handle this?

The IO assignment analysis is desperately trying to find IO pins for these ports. Is there a way to tell it which ports I want to leave unconnected to physical pins?

I get this error:

Error: Can't place 32 pins with 3.3-V LVCMOS I/O standard because Fitter has only 2 such free pins available for general purpose I/O placement

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Hi,

    as far as I know all signals in the top-level HDL entity must be assigned to physical pins.

    So my recommendation is to revise your top-level entity. Simply remove the signals that you don't need any more with the new FPGA. For input signals you must assign a default value, of course.

    If you want to keep both designs, you write a "wrapper" of your top level entity for the new FPGA, and assign the unused signals there.

    Best regards,

    GooGooCluster