How to handle too many pins in the design when migrating from Cyclone to Cyclone III

Hi,

as far as I know all signals in the top-level HDL entity must be assigned to physical pins.

So my recommendation is to revise your top-level entity. Simply remove the signals that you don't need any more with the new FPGA. For input signals you must assign a default value, of course.

If you want to keep both designs, you write a "wrapper" of your top level entity for the new FPGA, and assign the unused signals there.

Best regards,

GooGooCluster