Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

how to handle this critical warning related to pll

hii ,

in my design am using dadicated clock pin as a sourse to pll in cyclone iv fpga still m finding critical warning.

i tried back-annotation for all the banks still m getting same critical warning. in that case whatneeds to be done?????

Critical Warning (176598): PLL "syspll_usg:syspll_inst|altpll:altpll_component|syspll_usg_altpll:auto_generated|pll1" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_AA11"

thanks,

shaggy

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    That suggests you are feeding PLL1 from a pin that is not local to PLL1. It may well be a dedicated clock input pin but not one that is intended to feed that PLL.

    Each PLL will have one one more dedicated clock input pins that are intended for use with that PLL. However, some devices (depending on how many clocks and clock routing resource you're using) will allow you to route clocks (from dedicated clock input pins and others) to non-local PLLs.

    Is the dedicated clock pin you're using one you've specified? Try removing that constraint and let Quartus chose a pin for that clock input.

    Cheers,

    Alex