Honored Contributor
Honored ContributorI think I was not a bit clear in this case I am using A code in which I am instansiating a FIFO which is generated using altdpram,Now when I run Precision on it fllowed by Quartus place and route with the tcl file gnerated by precision ,Quartus gives a warning
Warning: Assertion warning: altdpram does not support Stratix II device family -- attempting best-case memory conversions, but power-up states and read during write behavior will be different for Stratix II devices And it takes Info: Implemented 17 input pins Info: Implemented 5 output pins Info: Implemented 5 RAM segments Now if I run the same design on Quartus II(integerated synthesis and place and route),it gives no such warning but instead gives the warning Warning:Design contains 17 input pins that do not derive logic. Info: Implemented 17 input pins Info: Implemented 5 output pins But no RAM segments. What could be the possible reason?
