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Altera_Forum's avatar
Altera_Forum
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14 years ago

How to give sdc constraint between CPU and IP.

Hi All,

I have designed one memory controller. I have used one PLL to generate clock frequency for my memory controller.When I compiled the system, I got almost 1000 paths between CPU and Memroy Controller which are violating set up or hold timings.I want to give false path between all the NIOS II signals to memory controller signals.I can't use set clock groups because PLL input clock and CPU clocks are the same.

Thanks in advance,

Regards,

Krupesh.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I suggest you to give an exception constraint between two different time domains: you may give

    set_clock_groups -asynchronous -group {clk_A} -group {clk_B}

    ---or---

    set_false_path -from clk_A -to clk_B

    set_false_path -to clk_A -from clk_B

    where clk_A and clk_B have been declared with create_clock or cretate_generated_clock or derive_pll_clocks (depending on your design).

    You ought to check your design contains proper synchronization among time domains.

    Regards,

    Gabriele
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Thanks for your reply Gabriele.

    I think I can't give constraint in that manner because my PLL input clock and CPU clock both are same. And I am generating my memory controller core from PLL. So if I assign set clock group between CPU clock and PLL generated clock then ultimately it will be same as to give false path between PLL input clock to PLL output clock. Correct me if I am wrong.

    Regards,

    Krupesh.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I must have missed a point:

    Which clock feeds the CPU logic?

    Which clock feeds the controller logic?

    Anyway, as generic suggestion:

    You may use another clock output from the PLL to feed the logic that is currently fed by pll inclk. Have you got any spare PLL output?