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Altera_Forum's avatar
Altera_Forum
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14 years ago

How to give sdc constraint between CPU and IP.

Hi All, I have designed one memory controller. I have used one PLL to generate clock frequency for my memory controller.When I compiled the system, I got almost 1000 paths between CPU and Memro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I must have missed a point:

Which clock feeds the CPU logic?

Which clock feeds the controller logic?

Anyway, as generic suggestion:

You may use another clock output from the PLL to feed the logic that is currently fed by pll inclk. Have you got any spare PLL output?