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Altera_Forum's avatar
Altera_Forum
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14 years ago

How to give sdc constraint between CPU and IP.

Hi All, I have designed one memory controller. I have used one PLL to generate clock frequency for my memory controller.When I compiled the system, I got almost 1000 paths between CPU and Memro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I suggest you to give an exception constraint between two different time domains: you may give

set_clock_groups -asynchronous -group {clk_A} -group {clk_B}

---or---

set_false_path -from clk_A -to clk_B

set_false_path -to clk_A -from clk_B

where clk_A and clk_B have been declared with create_clock or cretate_generated_clock or derive_pll_clocks (depending on your design).

You ought to check your design contains proper synchronization among time domains.

Regards,

Gabriele