How to give sdc constraint between CPU and IP.

Thanks for your reply Gabriele.

I think I can't give constraint in that manner because my PLL input clock and CPU clock both are same. And I am generating my memory controller core from PLL. So if I assign set clock group between CPU clock and PLL generated clock then ultimately it will be same as to give false path between PLL input clock to PLL output clock. Correct me if I am wrong.

Regards,

Krupesh.