How to generate Global RESET signal in Verilog?

Hi,

I want to generate a active LOW global reset signal once FPGA device power up.

I write my code like this:

reg [9:0] reset_sync_n = 1'b0; //initialize the reset signal

always @ (posedge CLK_50M) //Sync the reset signal to clock

begin

reset_sync_n <= 1'b1;

end

//reset_sync_n will be using as synchronous reset signal in others flip-flops logic like below:

always @ (posedge ref_clk)

begin

if (rst)

x <= 0;

else

x<= y;

end

My questions are:

1. Can the reset_sync_n initialized like the above? Will a active LOW reset signal be generated once FPGA device power up?

2. What is the right way to generate the RESET signal?

3. Asynchronous reset is better or synchronous reset is better? Which one is the better coding practice?

This is the doubts that always bother me. Please help me! Thank you!^^