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Honored Contributor
Honored ContributorHow to generate Global RESET signal in Verilog?
Hi, I want to generate a active LOW global reset signal once FPGA device power up. I write my code like this: reg [9:0] reset_sync_n = 1'b0; //initialize the reset signal al...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- In the top level, design a reset synchronizer which generates a synchronous reset signal. Connect that synchronized reset signal to your modules. A reset synchronizer should reset asynchronously, and set synchronously. --- Quote End --- There is no best way how to design the reset logic, however I also think that the above statement is a good practice. Thanks, Victor
