how to generate a post synthesis netlist without generating io buffer primitives

Hello , i use a stratix IV EP4SE530 and i generate a post synthesis netlist with quartus II avec cette commande

quartus_eda --resynthesis --tool=apsii --netlist=<output_netlist_file> <quartus ii project name>

This command generates a verilog post synthesis netlist which introduces basic primitives used on the design ( lut,flipflop,I/O buffers...)

I need an option that eliminate the generation of I/O buffers in this netlist.

I would like to generate a post mapping netlist without I/O buffers

thak you for your help